As electronics miniaturization, power consumption, and performance demands increase, the need for smaller, more efficient, digital to analog and analog to digital converters increases. Some applications include high fidelity audio, RF transmitters and receivers, frequency synthesizers, switched-mode power supplies and motor controls. Delta-sigma (ΔΣ) modulator analog to digital converters (ADCs) are employed in these data conversion applications. ADC circuits implementing ΔΣ modulation can achieve very high resolutions while using low-cost CMOS processes. The field of signal processing generally is demanding enhanced specifications including cost, complexity, power, speed, signal bandwidth, stability, oversampling ratio (OSR), output signal duty ratio, and signal to noise ratio (SNR). A notable measure is the signal-to-quantization-noise ratio (SQNR). SQNR represents the effect of quantization errors introduced by analog to digital conversion operations. A 6 dB improvement in the SQNR corresponds approximately to a one bit increase in resolution. Therefore, to achieve the higher resolutions required by today's applications, SQNR improvements are needed.
Delta-sigma modulators can control their SQNR in three ways. These methods include selecting appropriate values for 1) oversampling ratio, 2) modulator order, and 3) quantizer resolution. Higher performance is possible by increasing these values, but there are negative consequences. For example, increasing these values can require an increase the clock frequency and/or the number of devices, leading to greater power consumption and larger device size. While doubling the OSR can increase the SQNR for a second-order modulator, this places limitations on the input bandwidth. Increasing the modulator order has consequences of increased instability. Increasing quantizer resolution leads to a large die area and increased power consumption.
While zero optimization can increase ΔΣ modulator SQNR, especially for low OSR and high modulator orders, it too has negative consequences. With zero optimization, the zeros of the noise transfer function (NTF) can be placed at optimal frequencies for SQNR improvement. However, for high OSR, this technique results in very small values for the resonator coefficients. For example, a third-order prior art modulator shown in FIG. 1 with an OSR of 16 requires a coefficient of 0.022. FIG. 1 is a block diagram 100 of a prior art third-order modulator with zero optimization. Input U 105 is applied to summing nodes 110 and 115. Output of summing node 110 is applied to input of integrator 120. Output of integrator 120 is applied to input of feedforward path 125 and input of summing node 130. Output of summing node 130 is applied to input of integrator 135. Output of integrator 135 is applied to input of feedforward path 140 and input of integrator 145. Output of integrator 145 is applied to input of feedback path 150, whose output is applied to summing node 130. Output of integrator 145 is also applied to summing node 115, whose output is applied to quantizer 155. Quantizer output is returned to summing node 110 by digital output feedback path 160 and also provides output V 165.
The implementation of this small resonator coefficient value requires additional power consumption and larger die area, compared with the case without zero optimization. It can also be a cause of a high noise floor for the entire system. This might be solved by using a bigger capacitance or T-network, but either of these requires more power than the original modulator to reduce the noise floor. Generally, capacitors are scaled down from the first integrator (which is connected to the input signal) to the following integrators to save power. However, with zero optimization it is difficult to scale down the integrator capacitors while providing a small resonator feedback coefficient through one of the input branches. This is because the minimum allowable capacitance is decided by the fabrication process.
Generally, noise coupling is a technique to increase the order of modulators by adding and/or subtracting delayed quantization noise which allows better shaping of the quantization noise. Noise-coupled modulators can realize NTF zeros when implemented with the main modulator. However, for the main modulator, if a first-order modulator is used, only one zero can be moved. Hence, the SQNR improvement is not large compared with instead using a higher modulator order. Even with a second-order modulator, putting optimized zeros into the main transfer function is difficult because it requires a capacitance which is of the order of a few femtofarads. Additionally, the power consumption of the integrator (which has as one of its inputs the resonator feedback) is affected by this coefficient. Consequences are that a larger area and greater power consumption are required when increasing the capacitor sizes to obtain accurate capacitors.
What is needed are techniques for improving SQNR performance without degrading size, power consumption, stability, or bandwidth.